Exemplary embodiments relate generally to cache storage systems, and more particularly to dynamic pipeline cache error correction.
Technology advancements that allow larger and denser storage caches (e.g., static dynamic random access memory (SRAM) and embedded dynamic random access memory (eDRAM)) on a single chip are known to result in an increased number of soft errors. Soft errors refer to errors in a computer system which are not caused by a defect in design or manufacture. In other words, soft errors are errors that, if corrected, will go away, whereas defects in manufacturing or design will remain. These soft errors can be detected and corrected with error correction code (ECC) algorithms; however, because in many systems, it may be difficult to determine whether an error is present or to determine the correct data (e.g., after the system fails) the soft error goes undetected until the data is moved out of the cache during the correction process.
One known solution is to detect the error during array access pipe pass. This solution loads an engine that casts out a line of the cache in order to clean up the erroneous cache slot. However, as the number of soft errors increases, the number of unnecessary movement of data out of the cache increases also.